Dac Channel Modes - ST STM32G0 1 Series Reference Manual

Digital-to-analog converter (DAC)
16.4.11

DAC channel modes

Each DAC channel can be configured in Normal mode or Sample and hold mode. The
output buffer can be enabled to allow a high drive capability. Before enabling output buffer,
the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded
after reset) and can be adjusted by software during application operation.
Normal mode
In Normal mode, there are four combinations, by changing the buffer state and by changing
the DAC_OUTx pin interconnections.
To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
• 000: DAC is connected to the external pin
•
001: DAC is connected to external pin and to on-chip peripherals
To disable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
•
010: DAC is connected to the external pin
•
011: DAC is connected to on-chip peripherals
Sample and hold mode
In Sample and hold mode, the DAC core converts data on a triggered conversion, and then
holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer
are completely turned off between samples and the DAC output is tri-stated, therefore
reducing the overall power consumption. A stabilization period, which value depends on the
buffer state, is required before each new conversion.
In this mode, the DAC core and all corresponding logic and registers are driven by the LSI
low-speed clock (dac_hold_ck) in addition to the dac_pclk clock, allowing to use the DAC
channels in deep low power modes such as Stop mode.
The LSI low-speed clock (dac_hold_ck) must not be stopped when the Sample and hold
mode is enabled.
The sample/hold mode operations can be divided into 3 phases:
1. Sample phase: the sample/hold element is charged to the desired voltage. The
charging time depends on capacitor value (internal or external, selected by the user).
The sampling time is configured with the TSAMPLEx[9:0] bits in DAC_SHSRx register.
During the write of the TSAMPLEx[9:0] bits, the BWSTx bit in DAC_SR register is set to
1 to synchronize between both clocks domains (APB and low speed clock) and
allowing the software to change the value of sample phase during the DAC channel
operation
2. Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are
turned off, to reduce the current consumption. The hold time is configured with the
THOLDx[9:0] bits in DAC_SHHR register
3. Refresh phase: the refresh time is configured with the TREFRESHx[7:0] bits in
DAC_SHRR register
414/1390 RM0444 Rev 5
RM0444