Adc Watchdog Threshold Register (Adc_Awd3Tr); Adc Data Register (Adc_Dr) - ST STM32G0 1 Series Reference Manual

Analog-to-digital converter (ADC)

15.12.11 ADC watchdog threshold register (ADC_AWD3TR)

Address offset: 0x2C
Reset value: 0x0FFF 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT3[11:0]: Analog watchdog 3 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to
ADC_AWDxTR) on page
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT3[11:0]: Analog watchdog 3lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to
ADC_AWDxTR) on page

15.12.12 ADC data register (ADC_DR)

Address offset: 0x40
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Converted data
These bits are read-only. They contain the conversion result from the last converted channel. The data
are left- or right-aligned as shown in
OVSE = 0) on page
Just after a calibration is complete, DATA[6:0] contains the calibration factor.
398/1390
28 27 26 25
rw rw rw
12 11 10 9
rw rw rw
Section 15.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
369.
Section 15.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
369.
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
363.
24 23 22
HT3[11:0]
rw rw rw
8 7 6
LT3[11:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
DATA[15:0]
r r r
Figure 44: Data alignment and resolution (oversampling disabled:
RM0444 Rev 5
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
r r r r
RM0444
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
r r