Ucpd Control Register (Ucpd_Cr) - ST STM32G0 1 Series Reference Manual

USB Type-C™ / USB Power Delivery interface (UCPD)
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:25 TRIM2_NG_CC3A0[3:0]: SW trim value for RP3A0 resistors on the CC2 line
Bits 24:20 TRIM2_NG_CC1A5[4:0]: SW trim value for RP1A5 resistors on the CC2 line
Bits 19:16 TRIM2_NG_CCRPD[3:0]: SW trim value for RPD resistors on the CC2 line
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:9 TRIM1_NG_CC3A0[3:0]: SW trim value for RP3A0 resistors on the CC1 line
Bits 8:4 TRIM1_NG_CC1A5[4:0]: SW trim value for RP1A5 resistors on the CC1 line
Bits 3:0 TRIM1_NG_CCRPD[3:0]: SW trim value for RPD resistors on the CC1 line
38.7.4

UCPD control register (UCPD_CR)

Address offset: 0x00C
Reset value: 0x0000 0000
Writing to this register is only effective when the peripheral is enabled (UCPDEN = 1).
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 CC2TCDIS:CC2 Type-C detector disable
The bit disables the Type-C detector on the CC2 line.
0: Enable
1: Disable
When enabled, the Type-C detector for CC2 is configured through ANAMODE and
ANASUBMODE[1:0].
Bit 20 CC1TCDIS: CC1 Type-C detector disable
The bit disables the Type-C detector on the CC1 line.
0: Enable
1: Disable
When enabled, the Type-C detector for CC1 is configured through ANAMODE and
ANASUBMODE[1:0].
Bit 19 Reserved, must be kept at reset value.
1332/1390
28 27 26 25
Res. Res. Res.
12 11 10 9
CCENABLE[1:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
rw rw rw
RM0444 Rev 5
21 20 19 18
RDCH
rw rw rw
5 4 3 2
rw rw rs rs
RM0444
17 16
rs rw
1 0
TXMODE[1:0]
rw rw