Figure 236. Tim15 Block Diagram - ST STM32G0 1 Series Reference Manual

RM0444
XOR
TI1[0]
TIMx_CH1
TI1[1..15]
TI2[0]
TIMx_CH2
TI2
TI2[1..15]
Internal sources
TIMx_BKIN
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
1. The internal break event source can be:
- A clock failure event generated by CSS. For further information on the CSS, refer to
(CSS)
- A PVD output
- SRAM parity error signal
®
- Cortex -M0+ LOCKUP (Hardfault) output
- COMP output

Figure 236. TIM15 block diagram

Internal clock (CK_INT) from RCC
ITR0
ITR1
ITR2
ITR3
TI1F_ED
CK_PSC
TI1
Input
filter &
TI1FP1
IC1
edge
TI1FP2
detector
TRC
Input
TI2FP1
IC2
filter &
TI2FP2
edge
TRC
detector
SBIF
BIF
(1)
Break circuitry
General-purpose timers (TIM15/TIM16/TIM17)
TRG
ITR
TRC TRGI
TI1FP1
TI2FP2
U
Auto-reload register
Stop, clear or up/down
PSC CK_CNT
+/-
CNT counter
prescaler
CC1I
U
IC1PS
Capture/Compare 1 register
Prescaler
CC2I
U
IC2PS
Capture/Compare 2 register
Prescaler
BRK request
RM0444 Rev 5
Trigger
controller
TRGO
to other timers
Slave
Reset, enable, count
controller
mode
REP register
Repetition
counter
DTG registers
CC1I
OC1REF
Output
DTG
control
CC2I
Output
OC2REF
control
Section 5.2.9: Clock security system
(1)
UI
U
TIMx_CH1
OC1
TIMx_CH1N
OC1N
OC2
TIMx_CH2
MSv40934V5
743/1390
830