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System configuration controller (SYSCFG)
8.1.28
SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25)
Address offset: 0xE4
System reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SPI1: SPI1 interrupt request pending
8.1.29
SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26)
Address offset: 0xE8
System reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
1. Only significant on devices integrating SPI3, otherwise reserved. Refer to
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 SPI3: SPI3 interrupt request pending
Bit 0 SPI2: SPI2 interrupt request pending
8.1.30
SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27)
Address offset: 0xEC
System reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 USART1: USART1 interrupt request pending, combined with EXTI line 25
264/1390
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
Section 1.4: Availability of
(1)
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
RM0444 Rev 5
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
peripherals.
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
RM0444
17
16
Res.
Res.
1
0
Res.
SPI1
r
17
16
Res.
Res.
1
0
(1)
SPI2
SPI3
r
r
17
16
Res.
Res.
1
0
Res.
USART1
r
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