Figure 160. Control Circuit In External Clock Mode 2 + Trigger Mode - ST STM32G0 1 Series Reference Manual

RM0444
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
–
–
–
2. Configure the channel 1 as follows, to detect rising edges on TI:
–
–
–
–
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=00101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Counter clock = CK_CNT = CK_PSC
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.
ETF = 0000: no filter
ETPS = 00: prescaler disabled
ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
IC1F = 0000: no filter.
The capture prescaler is not used for triggering and does not need to be
configured.
CC1S = 01in TIMx_CCMR1 register to select only the input capture source
CC1P = 0 and CC1NP = 0 in TIMx_CCER register to validate the polarity (and
detect rising edge only).

Figure 160. Control circuit in external clock mode 2 + trigger mode

TI1
CEN/CNT_EN
ETR
Counter register
TIF
34
RM0444 Rev 5
Advanced-control timer (TIM1)
35 36
MS33110V1
581/1390
624