Clearing The Ocxref Signal On An External Event; Figure 194. Combined Pwm Mode On Channels 1 And 3 - ST STM32G0 1 Series Reference Manual

RM0444
When a given channel is used as combined PWM channel, its secondary channel must be
configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the
other in Combined PWM mode 2).
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
Figure 194
mode, obtained with the following configuration:
•
Channel 1 is configured in Combined PWM mode 2,
• Channel 2 is configured in PWM mode 1,
•
Channel 3 is configured in Combined PWM mode 2,
• Channel 4 is configured in PWM mode 1
OC2'
OC1'
OC2
OC1
OC1REF
OC2REF
OC1REF'
OC2REF'
OC1REFC
OC1REFC'
22.3.12

Clearing the OCxREF signal on an external event

The OCxREF signal of a given channel can be cleared when a high level is applied on the
ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).
OCxREF remains low until the next update event (UEV) occurs. This function can only be
used in Output compare and PWM modes. It does not work in Forced mode.
OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR
after the filter) by configuring the OCCS bit in the TIMx_SMCR register.
shows an example of signals that can be generated using Asymmetric PWM

Figure 194. Combined PWM mode on channels 1 and 3

OC1REFC = OC1REF AND OC2REF
OC1REFC' = OC1REF' OR OC2REF'
General-purpose timers (TIM2/TIM3/TIM4)
RM0444 Rev 5
MS31094V1
653/1390
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