Exti Registers; Exti Rising Trigger Selection Register (Exti_Rtsr1); Table 64. Exti Register Map Sections - ST STM32G0 1 Series Reference Manual

Extended interrupt and event controller (EXTI)
13.5

EXTI registers

The EXTI register map is divided in the following sections:
0x000 - 0x01C
0x060 - 0x06C
0x080 - 0x0BC
All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit)
access.
13.5.1

EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29
Res. Res. Res. Res.
15 14 13
RT15 RT14 RT13 RT12
rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 RT20: Rising trigger event configuration bit of configurable line 20
Bit 19 Reserved, must be kept at reset value.
Bits 18:0 RTx: Rising trigger event configuration bit of configurable line x (x = 18 to 0)
1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger.
324/1390

Table 64. EXTI register map sections

Address
General configurable event [31:0] configuration
EXTI I/O port multiplexer
CPU input event configuration
28 27 26 25
Res. Res. Res.
12 11 10 9
RT11 RT10 RT9
rw rw rw rw
This bit enables/disables the rising edge trigger for the event and interrupt on the
corresponding line.
0: Disable
1: Enable
The RT20 bit is only available in STM32G0B1xx and STM32G0C1xx. It is reserved in all the
other devices.
Each bit enables/disables the rising edge trigger for the event and interrupt on the
corresponding line.
0: Disable
1: Enable
The RT18 and RT17 bits are only available in STM32G071xx and STM32G081xx as well as
STM32G0B1xx and STM32G0C1xx. They are reserved in STM32G031xx and
STM32G041xx as well as STM32G051xx and STM32G061xx.
Description
24 23 22
Res. Res. Res. Res.
8 7 6
RT8 RT7 RT6
rw rw rw
RM0444 Rev 5
21 20 19 18
RT20 Res. RT18
rw rw
5 4 3 2
RT5 RT4 RT3 RT2
rw rw rw rw
(1)
(2)
RM0444
17 16
RT17 RT16
rw rw
1 0
RT1 RT0
rw rw