Embedded Flash memory (FLASH)
3.7.16
FLASH PCROP2 area A end address register
(FLASH_PCROP2AER)
Address offset: 0x048
Reset value: 0bX000 0000 0000 0000 0000 000X XXXX XXXX (The option bits are loaded
with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word access.
PCROP_RDP bit can be accessed with byte access
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept cleared
Bits 8:0 PCROP2A_END[8:0]: PCROP2A area end offset, Bank 2
1. The number of effective bits depends on the size of Flash memory in the device.
3.7.17
FLASH WRP2 area A address register (FLASH_WRP2AR)
Address offset: 0x04C
Reset value: 0b0000 0000 0XXX XXXX 0000 0000 0XXX XXXX (The option bits are loaded
with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access.
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 WRP2A_END[6:0]: WRP area A end offset, Bank 2
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP2A_STRT[6:0]: WRP area A start offset, Bank 2
1. The number of effective bits depends on the size of Flash memory in the device.
114/1390
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Contains the offset of the last subpage of the PCROP2A area in Bank 2.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
This bitfield contains the offset of the last page of the WRP area A in Bank 2.
This bitfield contains the offset of the first page of the WRP area A in Bank 2.
24
23
22
Res.
Res.
Res.
8
7
6
rw
rw
rw
24
23
22
Res.
Res.
rw
8
7
6
Res.
Res.
rw
RM0444 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PCROP2A_END[8:0]
rw
rw
rw
rw
(1)
21
20
19
18
WRP2A_END[6:0]
rw
rw
rw
rw
5
4
3
2
WRP2A_STRT[6:0]
rw
rw
rw
rw
RM0444
17
16
Res.
Res.
1
0
rw
rw
17
16
rw
rw
1
0
rw
rw
(1)
(1)
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