Fdcan Nominal Bit Timing And Prescaler Register (Fdcan_Nbtp) - ST STM32G0 1 Series Reference Manual

FD controller area network (FDCAN)
Bit 2 ASM: ASM restricted operation mode
The restricted operation mode is intended for applications that adapt themselves to different
CAN bit rates. The application tests different bit rates and leaves the Restricted Operation
Mode after it has received a valid frame. In the optional Restricted Operation Mode the node
is able to transmit and receive data and remote frames and it gives acknowledge to valid
frames, but it does not send active error frames or overload frames. In case of an error
condition or overload condition, it does not send dominant bits, instead it waits for the
occurrence of bus idle condition to resynchronize itself to the CAN communication. The error
counters are not incremented. Bit ASM can only be set by software when both CCE and INIT
are set to 1. The bit can be reset by the software at any time.
0: Normal CAN operation
1: Restricted Operation Mode active
Bit 1 CCE: Configuration change enable
0: The CPU has no write access to the protected configuration registers.
1: The CPU has write access to the protected configuration registers (while CCCR.INIT = 1).
Bit 0 INIT: Initialization
0: Normal operation
1: Initialization started
Note: Due to the synchronization mechanism between the two clock domains, there may be a
delay until the value written to INIT can be read back. Therefore the programmer has to
assure that the previous value written to INIT has been accepted by reading INIT before
setting INIT to a new value.
36.4.7

FDCAN nominal bit timing and prescaler register (FDCAN_NBTP)

Address offset: 0x001C
Reset value: 0x0600 0A03
This register is only writable if bits CCCR[CCE] and CCCR[INIT] are set. The CAN bit time
may be programed in the range of 4 to 81 tq. The CAN time quantum may be programmed
in the range of [1 ... 1024] FDCAN kernel clock periods.
tq = (BRP + 1) FDCAN clock period fdcan_clk
NTSEG1 is the sum of Prop_Seg and Phase_Seg1. NTSEG2 is Phase_Seg2. Therefore the
length of the bit time is (programmed values) [NTSEG1 + NTSEG2 + 3] tq or (functional
values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.
The Information Processing Time (IPT) is 0, meaning the data for the next bit is available at
the first clock edge after the sample point.
31 30 29
NSJW[6:0]
rw rw rw
15 14 13
rw rw rw
1232/1390
28 27 26 25
rw rw rw rw
12 11 10 9
NTSEG1[7:0]
rw rw rw rw
24 23 22
rw rw rw
8 7 6
Res.
rw rw
RM0444 Rev 5
21 20 19 18
NBRP[8:0]
rw rw rw rw
5 4 3 2
NTSEG2[6:0]
rw rw rw rw
RM0444
17 16
rw rw
1 0
rw rw