Crs Registers; Crs Control Register (Crs_Cr) - ST STM32G0 1 Series Reference Manual

Clock recovery system (CRS)
6.7

CRS registers

Refer to
The peripheral registers can be accessed only by words (32-bit).
6.7.1

CRS control register (CRS_CR)

Address offset: 0x00
Reset value: 0x0000 X000 (X=4 for products supporting 7-bit TRIM width, otherwise X=2)
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res.
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Bits 31:15 Reserved, must be kept at reset value.
Bits 14:8 TRIM[6:0]: HSI48 oscillator smooth trimming
Bit 7 SWSYNC: Generate software SYNC event
Bit 6 AUTOTRIMEN: Automatic trimming enable
Bit 5 CEN: Frequency error counter enable
Bit 4 Reserved, must be kept at reset value.
Bit 3 ESYNCIE: Expected SYNC interrupt enable
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Section 1.2 on page 53
27 26 25
Res. Res. Res.
11 10 9
TRIM[6:0]
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For product supporting the 7-bit TRIM width (see
oscillator smooth trimming is 64, which corresponds to the middle of the trimming interval.
For products supporting the 6-bit TRIM width (see
kept at reset value.
This bit is set by software in order to generate a software SYNC event. It is automatically
cleared by hardware.
0: No action
1: A software SYNC event is generated.
This bit enables the automatic hardware adjustment of TRIM bits according to the measured
frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The
TRIM value can be adjusted by hardware by one or two steps at a time, depending on the
measured frequency error value. Refer to
0: Automatic trimming disabled, TRIM bits can be adjusted by the user.
1: Automatic trimming enabled, TRIM bits are read-only and under hardware control.
This bit enables the oscillator clock for the frequency error counter.
0: Frequency error counter disabled
1: Frequency error counter enabled
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.
0: Expected SYNC (ESYNCF) interrupt disabled
1: Expected SYNC (ESYNCF) interrupt enabled
for a list of abbreviations used in register descriptions.
24 23 22 21
Res. Res. Res. Res.
8 7 6
SW AUTO
CEN
SYNC TRIMEN
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Section
Section 6.4.4
RM0444 Rev 5
20 19 18
Res. Res. Res.
5 4 3 2
ESYNCI
Res. ERRIE
E
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6.3), the default value of the HSI48
Section 6.3) this bit is reserved, must be
for more details.
RM0444
17 16
Res. Res.
1 0
SYNC SYNC
WARNIE OKIE
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