Tim1 Capture/Compare Register 5 (Tim1_Ccr5) - ST STM32G0 1 Series Reference Manual

RM0444
Bits 31:25 Reserved, must be kept at reset value.
Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC6CE: Output compare 6 clear enable
Refer to OC1CE description.
Bits 24, 14, 13, 12 OC6M[3:0]: Output compare 6 mode
Refer to OC1M description.
Bit 11 OC6PE: Output compare 6 preload enable
Refer to OC1PE description.
Bit 10 OC6FE: Output compare 6 fast enable
Refer to OC1FE description.
Bits 9:8 Reserved, must be kept at reset value.
Bit 7 OC5CE: Output compare 5 clear enable
Refer to OC1CE description.
Bits 16, 6, 5, 4 OC5M[3:0]: Output compare 5 mode
Refer to OC1M description.
Bit 3 OC5PE: Output compare 5 preload enable
Refer to OC1PE description.
Bit 2 OC5FE: Output compare 5 fast enable
Refer to OC1FE description.
Bits 1:0 Reserved, must be kept at reset value.
21.4.25

TIM1 capture/compare register 5 (TIM1_CCR5)

Address offset: 0x58
Reset value: 0x0000 0000
31 30 29
GC5C3 GC5C2 GC5C1 Res.
rw rw rw
15 14 13
rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
CCR5[15:0]
rw rw rw
RM0444 Rev 5
Advanced-control timer (TIM1)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
615/1390
624