Timx Auto-Reload Register (Timx_Arr)(X = 2 To 4); Timx Capture/Compare Register 1 (Timx_Ccr1)(X = 2 To 4) - ST STM32G0 1 Series Reference Manual

RM0444
Bits 15:0 PSC[15:0]: Prescaler value
22.4.15

TIMx auto-reload register (TIMx_ARR)(x = 2 to 4)

Address offset: 0x2C
Reset value: 0xFFFF FFFF
31 30 29
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15 14 13
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Bits 31:16 ARR[31:16]: High auto-reload value (TIM2)
Bits 15:0 ARR[15:0]: Low Auto-reload value
22.4.16

TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 4)

Address offset: 0x34
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
28 27 26 25
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12 11 10 9
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ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 22.3.1: Time-base unit on page 627
and behavior.
The counter is blocked while the auto-reload value is null.
27 26 25
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11 10 9
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General-purpose timers (TIM2/TIM3/TIM4)
CK_PSC
24 23 22
ARR[31:16]
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8 7 6
ARR[15:0]
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24 23 22
CCR1[31:16]
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8 7 6
CCR1[15:0]
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RM0444 Rev 5
/ (PSC[15:0] + 1).
21 20 19 18
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5 4 3 2
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for more details about ARR update
21 20 19 18
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5 4 3 2
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17 16
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1 0
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17 16
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1 0
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689/1390
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