Pll Configuration Register (Rcc_Pllcfgr) - ST STM32G0 1 Series Reference Manual

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Bits 11:8 HPRE[3:0]: AHB prescaler

Caution: Depending on the device voltage range, the software has to set correctly these bits to

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:3 SWS[2:0]: System clock switch status

Bits 2:0 SW[2:0]: System clock switch

PLL configuration register (RCC_PLLCFGR)

Address offset: 0x0C

Reset value: 0x0000 1000

This register configures the PLL clock outputs according to the formulas:

This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of

SYSCLK clock as follows:

ensure that the system frequency does not exceed the maximum allowed frequency

(for more details, refer to

a write operation to these bits and before decreasing the voltage range, this register

must be read to be sure that the new value has been taken into account.

This bitfield is controlled by hardware to indicate the clock source used as system clock:

010: PLLRCLK

Others: Reserved

This bitfield is controlled by software and hardware. The bitfield selects the clock for

SYSCLK as follows:

010: PLLRCLK

Others: Reserved

The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop,

Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator

failure is detected.

Section 4.1.4: Dynamic voltage scaling

RM0444 Rev 5

Reset and clock control (RCC)

management). After

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