Syscfg Interrupt Line 23 Status Register (Syscfg_Itline23); Syscfg Interrupt Line 24 Status Register (Syscfg_Itline24) - ST STM32G0 1 Series Reference Manual

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1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to

peripherals.

Bits 31:1 Reserved, must be kept at reset value.

Bit 2 FDCAN2_IT1: FDCAN2 interrupt request pending

Bit 1 FDCAN1_IT1: FDCAN1 interrupt request pending

Bit 0 TIM17: Timer 17 interrupt request pending

SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23)

Address offset: 0xDC

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 I2C1: I2C1 interrupt request pending, combined with EXTI line 23

Address offset: 0xE0

System reset value: 0x0000 0000

1. Only significant on devices integrating I2C3, otherwise reserved. Refer to

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 I2C3: I2C3 interrupt request pending (EXTI line 22)

Bit 0 I2C2: I2C2 interrupt request pending

System configuration controller (SYSCFG)

Section 1.4: Availability of

RM0444 Rev 5

Section 1.4: Availability

peripherals.

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