Exti Software Interrupt Event Register 2 (Exti_Swier2); Exti Rising Edge Pending Register 2 (Exti_Rpr2) - ST STM32G0 1 Series Reference Manual

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Bits 31:3 Reserved, must be kept at reset value.

Bit 2 FT2: Falling trigger event configuration bit of configurable line 34

Bits 1:0 Reserved, must be kept at reset value.

1. The configurable lines are edge triggered, no glitch must be generated on these inputs.

If a falling edge on the configurable line occurs during writing of the register, the associated pending bit is not set.

Falling edge trigger can be set for a line with rising edge trigger enabled. In this case, both edges generate a trigger.

EXTI software interrupt event register 2 (EXTI_SWIER2)

Address offset: 0x030

Reset value: 0x0000 0000

Contains only register bits for configurable events.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 SWI2: Software rising edge event trigger on line 34)

Bits 1:0 Reserved, must be kept at reset value.

Address offset: 0x034

This bit enables/disables the falling edge trigger for the event and interrupt on the

corresponding line.

The FT2 bit is only available in STM32G0B1xx and STM32G0C1xx. This bit is reserved in all

the other devices.

Setting of any bit by software triggers a rising edge event on the line 34, resulting in an

interrupt, independently of EXTI_RTSR2 and EXTI_FTSR2 settings. This bit is automatically

cleared by hardware. Reading the bit always returns 0.

0: No effect

1: Rising edge event generated on the corresponding line, followed by an interrupt

The SWI2 bit is only available in STM32G0B1xx and STM32G0C1xx. This bit is reserved in

all the other devices.

Extended interrupt and event controller (EXTI)

RM0444 Rev 5

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