I2C Pins And Internal Signals; I2C Clock Requirements; Mode Selection; Table 162. I2C Input/Output Pins - ST STM32G0 1 Series Reference Manual

RM0444
32.4.3

I2C pins and internal signals

Pin name
I2C_SDA
I2C_SCL
I2C_SMBA
Internal signal name
i2c_ker_ck
i2c_pclk
i2c_it
i2c_rx_dma
i2c_tx_dma
32.4.4

I2C clock requirements

The I2C kernel is clocked by I2CCLK.
The I2CCLK period t
t < (t
I2CCLK
with:
t : SCL low time and t
LOW
t when enabled, sum of the delays brought by the analog filter and by the digital filter.
filters:
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x t
The PCLK clock period t
t < 4/3 t
PCLK
with t
SCL
Caution: When the I2C kernel is clocked by PCLK, this clock must respect the conditions for t
32.4.5

Mode selection

The interface can operate in one of the four following modes:
•
Slave transmitter
•
Slave receiver
•
Master transmitter
•
Master receiver

Table 162. I2C input/output pins

Bidirectional
Bidirectional
Bidirectional

Table 163. I2C internal input/output signals

Input
Input
Output
Output
Output
must respect the following conditions:
I2CCLK
- t ) / 4 and t
LOW filters
: SCL high time
HIGH
must respect the following condition:
PCLK
SCL
: SCL period
Inter-integrated circuit (I2C) interface
Signal type
I2C data
I2C clock
SMBus Alert
Signal type
I2C kernel clock, also named I2CCLK in this
document
I2C APB clock
I2C interrupts, refer to
requests
I2C Receive Data DMA request (I2C_RX)
I2C Transmit Data DMA request (I2C_TX)
< t
I2CCLK HIGH
RM0444 Rev 5
Description
Description
Table 177: I2C Interrupt
for the full list of interrupt sources
.
I2CCLK
.
I2CCLK
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