I2C Timeout Register (I2C_Timeoutr) - ST STM32G0 1 Series Reference Manual

Inter-integrated circuit (I2C) interface
32.7.6

I2C timeout register (I2C_TIMEOUTR)

Address offset: 0x14
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.
31 30 29
TEXTEN Res. Res.
rw
15 14 13
TIMOUTEN Res. Res.
rw
Bit 31 TEXTEN: Extended clock timeout enable
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 TIMEOUTB[11:0]: Bus timeout B
Note: These bits can be written only when TEXTEN=0.
Bit 15 TIMOUTEN: Clock timeout enable
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 TIDLE: Idle clock timeout detection
Note: This bit can be written only when TIMOUTEN=0.
Bits 11:0 TIMEOUTA[11:0]: Bus Timeout A
Note: These bits can be written only when TIMOUTEN=0.
Note:
If the SMBus feature is not supported,
"0x00000000".
990/1390
28 27 26
Res.
rw rw
12 11 10
TIDLE
rw rw rw
0: Extended clock timeout detection is disabled
1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more
than t is done by the I2C interface, a timeout error is detected (TIMEOUT=1).
LOW:EXT
This field is used to configure the cumulative clock extension timeout:
In master mode, the master cumulative clock low extend time (t
In slave mode, the slave cumulative clock low extend time (t
t = (TIMEOUTB+1) x 2048 x t
LOW:EXT
0: SCL timeout detection is disabled
1: SCL timeout detection is enabled: when SCL is low for more than t
high for more than t
IDLE
0: TIMEOUTA is used to detect SCL low timeout
1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
This field is used to configure:
The SCL low timeout condition t
t = (TIMEOUTA+1) x 2048 x t
TIMEOUT
The bus idle condition (both SCL and SDA high) when TIDLE=1
t = (TIMEOUTA+1) x 4 x t
IDLE
Refer to Section 32.3: I2C
25 24 23
TIMEOUTB[11:0]
rw rw rw
9 8 7
TIMEOUTA[11:0]
rw rw rw
I2CCLK
(TIDLE=1), a timeout error is detected (TIMEOUT=1).
when TIDLE=0
TIMEOUT
I2CCLK
I2CCLK
this register is reserved and forced by hardware to
implementation.
RM0444 Rev 5
22 21 20 19
rw rw rw rw
6 5 4 3
rw rw rw rw
LOW:MEXT
) is detected
LOW:SEXT
TIMEOUT
RM0444
18 17 16
rw rw rw
2 1 0
rw rw rw
) is detected
(TIDLE=0) or