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System configuration controller (SYSCFG)
8.1.17
SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14)
Address offset: 0xB8
System reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 TIM1_CC: Timer 1 capture compare interrupt request pending
8.1.18
SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15)
Address offset: BCh
System reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 TIM2: Timer 2 interrupt request pending
8.1.19
SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16)
Address offset: 0xC0
System reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
1. Only significant on devices integrating TIM4, otherwise reserved. Refer to
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 TIM4: Timer 4 interrupt request pending
Bit 0 TIM3: Timer 3 interrupt request pending
260/1390
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
Section 1.4: Availability of
RM0444 Rev 5
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
peripherals.
RM0444
17
16
Res.
Res.
1
0
TIM1_
Res.
CC
r
17
16
Res.
Res.
1
0
Res.
TIM2
r
17
16
Res.
Res.
1
0
(1)
TIM3
TIM4
r
r
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