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System configuration controller (SYSCFG)
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
1. Only significant on devices integrating CEC, otherwise reserved. Refer to
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 CEC: CEC interrupt request pending (EXTI line 27)
8.1.34
SYSCFG interrupt line 31 status register (SYSCFG_ITLINE31)
Address offset: 0xFC
System reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
1. Onldy significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to
of
peripherals.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 AES: AES interrupt request pending
Bit 0 RNG: RNG interrupt request pending
8.1.35
SYSCFG register map
The following table gives the SYSCFG register map and the reset values.
Offset
Register
SYSCFG_CFGR1
0x00
Reset value
0x04 to
Reserved
0x17
266/1390
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
Table 44. SYSCFG register map and reset values
0
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Section 1.4: Availability of
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
(1)
(1)
0
0
0
0
0
0
0
0
Reserved
RM0444 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
peripherals.
(1)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
Section 1.4: Availability
0
0
0
0
RM0444
17
16
Res.
Res.
1
0
(1)
Res.
CEC
r
17
16
Res.
Res.
1
0
(1)
(1)
AES
RNG
r
r
0
0
0
0
X X
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