Ucpd Registers; Ucpd Configuration Register 1 (Ucpd_Cfgr1) - ST STM32G0 1 Series Reference Manual

RM0444
38.7

UCPD registers

38.7.1

UCPD configuration register 1 (UCPD_CFGR1)

Address offset: 0x000
Reset value: 0x0000 0000
General configuration of the peripheral. Writing to this register is only effective when UCPD
is disabled (UCPDEN = 0).
31 30 29
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15 14 13
TRANSWIN[4:0]
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Bit 31 UCPDEN: UCPD peripheral enable
General enable of the UCPD peripheral.
0: Disable
1: Enable
Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and
bitfields default to their reset values. They must be set to their desired values each time the
peripheral transits from disabled to enabled state.
Bit 30 RXDMAEN: Reception DMA mode enable
When set, the bit enables DMA mode for reception.
0: Disable
1: Enable
Bit 29 TXDMAEN: Transmission DMA mode enable
When set, the bit enables DMA mode for transmission.
0: Disable
1: Enable
Bits 28:20 RXORDSETEN[8:0]: Receiver ordered set enable
The bitfield determines the types of ordered sets that the receiver must detect. When
set/cleared, each bit enables/disables a specific function:
0bxxxxxxxx1: SOP detect enabled
0bxxxxxxx1x: SOP' detect enabled
0bxxxxxx1xx: SOP'' detect enabled
0bxxxxx1xxx: Hard Reset detect enabled
0bxxxx1xxxx: Cable Detect reset enabled
0bxxx1xxxxx: SOP'_Debug enabled
0bxx1xxxxxx: SOP''_Debug enabled
0bx1xxxxxxx: SOP extension#1 enabled
0b1xxxxxxxx: SOP extension#2 enabled
28 27 26 25
RXORDSETEN[8:0]
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12 11 10 9
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USB Type-C™ / USB Power Delivery interface (UCPD)
24 23 22
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8 7 6
IFRGAP[4:0]
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RM0444 Rev 5
21 20 19 18
PSC_USBPDCLK[2:0]
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5 4 3 2
HBITCLKDIV[5:0]
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17 16
Res.
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1 0
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1329/1390
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