Lpuart Control Register 2 (Lpuart_Cr2) - ST STM32G0 1 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
Bit 3 TE: Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: During transmission, a low pulse on the TE bit ("0" followed by "1") sends a preamble
Bit 2 RE: Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 UESM: LPUART enable in Stop mode
When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode.
When this bit is set, the LPUART is able to wake up the MCU from low-power mode,
provided that the LPUART clock selection is HSI or LSE in the RCC.
This bit is set and cleared by software.
0: LPUART not able to wake up the MCU from low-power mode.
1: LPUART able to wake up the MCU from low-power mode. When this function is active,
the clock source for the LPUART must be HSI or LSE (see RCC chapter)
Note: It is recommended to set the UESM bit just before entering low-power mode and clear
Bit 0 UE: LPUART enable
When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and
current operations are discarded. The configuration of the LPUART is kept, but all the status
flags, in the LPUART_ISR are reset. This bit is set and cleared by software.
0: LPUART prescaler and outputs disabled, low-power mode
1: LPUART enabled
Note: To enter low-power mode without generating errors on the line, the TE bit must be reset
34.7.3

LPUART control register 2 (LPUART_CR2)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
SWAP Res. STOP[1:0]
rw rw
1120/1390
(idle line) after the current word. In order to generate an idle character, the TE must not
be immediately written to 1. In order to ensure the required duration, the software can
poll the TEACK bit in the LPUART_ISR register.
When TE is set there is a 1 bit-time delay before the transmission starts.
it on exit from low-power mode.
before and the software must wait for the TC bit in the LPUART_ISR to be set before
resetting the UE bit.
The DMA requests are also reset when UE = 0 so the DMA channel must be disabled
before resetting the UE bit.
28 27 26 25
ADD[7:0]
rw rw rw rw
12 11 10 9
Res. Res. Res.
rw
24 23 22
Res. Res. Res.
rw
8 7 6
Res. Res. Res. Res.
RM0444 Rev 5
21 20 19 18
MSBFI
Res. DATAINV TXINV
RST
rw rw
5 4 3 2
ADDM7 Res. Res.
rw
RM0444
17 16
RXINV
rw rw
1 0
Res. Res.