I/O Port Reset Register (Rcc_Ioprstr); Ahb Peripheral Reset Register (Rcc_Ahbrstr) - ST STM32G0 1 Series Reference Manual

Reset and clock control (RCC)
5.4.9

I/O port reset register (RCC_IOPRSTR)

Address: 0x24
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to
of peripherals.
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 GPIOFRST: I/O port F reset
Bit 4 GPIOERST: I/O port E reset
Bit 3 GPIODRST: I/O port D reset
Bit 2 GPIOCRST: I/O port C reset
Bit 1 GPIOBRST: I/O port B reset
Bit 0 GPIOARST: I/O port A reset
5.4.10

AHB peripheral reset register (RCC_AHBRSTR)

Address offset: 0x28
Reset value: 0x0000 0000
190/1390
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit is set and cleared by software.
0: no effect
1: Reset I/O port F
This bit is set and cleared by software.
0: no effect
1: Reset I/O port E
This bit is set and cleared by software.
0: no effect
1: Reset I/O port D
This bit is set and cleared by software.
0: no effect
1: Reset I/O port C
This bit is set and cleared by software.
0: no effect
1: Reset I/O port B
This bit is set and cleared by software.
0: no effect
1: Reset I/O port A
24 23 22
Res. Res. Res. Res.
8 7 6
GPIOF
Res. Res. Res.
RST
(1)
RM0444 Rev 5
21 20 19 18
Res. Res. Res.
5 4 3 2
GPIOE
GPIOD GPIOC
(1)
RST RST
RST
rw rw rw rw
Section 1.4: Availability
RM0444
17 16
Res. Res.
1 0
GPIOB GPIOA
RST RST
rw rw