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RM0444
22.4.26
TIM3 alternate function option register 1 (TIM3_AF1)
Address offset: 0x60
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
ETRSEL[1:0]
Res.
Res.
rw
rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:14 ETRSEL[3:0]: ETR source selection
Bits 13:0 Reserved, must be kept at reset value.
1. Available on STM32G0B1xx and STM32G0C1xx salestypes only.
22.4.27
TIM4 alternate function option register 1 (TIM4_AF1)
Address offset: 0x60
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
ETRSEL[1:0]
Res.
Res.
rw
rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:14 ETRSEL[3:0]: ETR source selection
Bits 13:0 Reserved, must be kept at reset value.
1. Available on STM32G0B1xx and STM32G0C1xx salestypes only.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
These bits select the ETR input source.
0000: ETR legacy mode
0001: COMP1 output
0010: COMP2 output
(1)
0110: COMP3 output
Others: Reserved
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
These bits select the ETR input source.
0000: ETR legacy mode
0001: COMP1 output
0010: COMP2 output
(1)
0110: COMP3 output
Others: Reserved
General-purpose timers (TIM2/TIM3/TIM4)
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0444 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
ETRSEL[3:2]
rw
rw
1
0
Res.
Res.
17
16
ETRSEL[3:2]
rw
rw
1
0
Res.
Res.
695/1390
701
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