Gpio Port Configuration Lock Register (Gpiox_Lckr); (X = A To F) - ST STM32G0 1 Series Reference Manual

General-purpose I/Os (GPIO)
15 14 13
BS15 BS14 BS13 BS12
w w w
Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
7.4.8

GPIO port configuration lock register (GPIOx_LCKR)

(x = A to F)

This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
LCK15 LCK14 LCK13 LCK12
rw rw rw
244/1390
12 11 10 9
BS11 BS10 BS9
w w w w
0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
LCK11 LCK10 LCK9
rw rw rw rw
8 7 6
BS8 BS7 BS6
w w w
24 23 22
Res. Res. Res.
8 7 6
LCK8 LCK7 LCK6
rw rw rw
RM0444 Rev 5
5 4 3 2
BS5 BS4 BS3 BS2
w w w w
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
LCK5 LCK4 LCK3 LCK2
rw rw rw rw
RM0444
1 0
BS1 BS0
w w
17 16
Res. LCKK
rw
1 0
LCK1 LCK0
rw rw