Exti Register Map; Table 65. Exti Controller Register Map And Reset Values - ST STM32G0 1 Series Reference Manual

Extended interrupt and event controller (EXTI)
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 EMx: CPU wakeup with event generation mask on line x (x = 35 to 32)
Setting/clearing each bit unmasks/masks the CPU wakeup with event generation on the
corresponding line.
0: wakeup with event generation masked
1: wakeup with event generation unmasked
The EM35 and EM34 bits are only available in STM32G0B1xx and STM32G0C1xx. They
are reserved in STM32G071xx and STM32G081xx.
13.5.16

EXTI register map

The following table gives the EXTI register map and the reset values.
Offset Register
EXTI_RTSR1
0x000
Reset value
EXTI_FTSR1
0x004
Reset value
EXTI_SWIER1
0x008
Reset value
EXTI_RPR1
0x00C
Reset value
EXTI_FPR1
0x010
Reset value
0x014-
Reserved
0x024
EXTI_RTSR2
0x028
Reset value
EXTI_FTSR2
0x02C
Reset value
EXTI_SWIER2
0x030
Reset value
EXTI_RPR2
0x034
Reset value
EXTI_FPR2
0x038
Reset value
0x038-
Reserved
0x05C
334/1390

Table 65. EXTI controller register map and reset values

0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
RM0444 Rev 5
RT[18:0]
0 0 0 0 0 0 0 0 0
FT[18:0]
0 0 0 0 0 0 0 0 0
SWI[18:0]
0 0 0 0 0 0 0 0 0
RPIF[18:0]
0 0 0 0 0 0 0 0 0
FPIF[16:0]
Res.
0 0 0 0 0 0 0 0 0
RM0444
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0
0
0
0
0