Dac Functional Description; Dac Block Diagram - ST STM32G0 1 Series Reference Manual

Digital-to-analog converter (DAC)
16.4

DAC functional description

16.4.1

DAC block diagram

dac_ch1_trg1
dac_ch1_trg15
dac_ch1_dma
dac_unr_it
dac_pclk
dac_hold
_ck
dac_ch2_dma
dac_ch2_trg1
dac_ch2_trg15
dac_hold
_ck
1. MODEx bits in the DAC_MCR control the output mode and allow switching between the Normal mode in
buffer/unbuffered configuration and the Sample and hold mode.
2. Refer to
406/1390
Figure 59. Dual-channel DAC block diagram
TRIG
TSEL1
[3:0]
bits
Control registers
& logic Channel1
DAC channel 1
Control registers
& logic Channel2
TSEL2
[3:0] bits
TRIG
DAC channel 2
Section 16.3: DAC implementation
VDD
Offset
calibration
OTRIM1[5:0]
bits
MODE1 bits
DOR1
converter 1
12-bit
Sample & Hold registers
TSAMPLE1
THOLD1
TREFRESH1
Offset
calibration
OTRIM2[5:0]
bits
MODE2 bits
DOR2
converter 2
12-bit
Sample & Hold registers
TSAMPLE2
THOLD2
TREFRESH2
VSS
for channel2 availability.
RM0444 Rev 5
Buffer
DAC
1
Buffer
DAC
2
RM0444
dac_out1
dac_out2
MSv46119V5