Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 99

PCH Pin States
Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations
(Sheet 5 of 6)
Signal Name
9
GPIO31 (Non Deep-S4/
S5 mode)
9
GPIO31 (Deep-S4/S5
mode)
9
GPIO33
GPIO35
SPI_CS0#
7
SPI_CS1#
7
SPI_MOSI
SPI_CLK
6
CL_CLK1
6
CL_DATA1
6
CL_RST1#
PECI
VGA_RED, VGA_GREEN,
VGA_BLUE
DAC_IREF
VGA_HSYNC
VGA_VSYNC
VGA_DDC_CLK
VGA_DDC_DATA
VGA_IRTN
FDI_FSYNC[1:0]
FDI_LSYNC[1:0]
FDI_INT
Datasheet
Power During
1
Plane Reset
DSW High-Z (Input)
DSW High-Z (Input)
Core High
Core Low
SPI Interface
12
ASW High
12
ASW High
12
ASW Low
12
ASW Low
Controller Link
15
Suspend High/Low
15
Suspend High/Low
Suspend Low
Thermal Signals
Processor Low
Analog Display / CRT DAC Signals
Core High-Z
Core High-Z
Core Low
Core Low
Core High-Z
Core High-Z
Core High-Z
®
Intel Flexible Display Interface
Core High-Z
Core High-Z
Core High-Z
Immediately
S0/S1
1
after Reset
High-Z (Input) Defined
High-Z (Input) Defined
High High
Low Defined
High Defined
High Defined
Low Defined
Low Running
15
High/Low Defined
15
High/Low Defined
High High
Low Defined
High-Z High-Z
Low Low
Low Low
Low Low
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
S3 S4/S5
Defined Defined
Defined Defined
Off Off
Off Off
Defined Defined
Defined Defined
Defined Defined
Defined Defined
Defined Defined
Defined Defined
High High
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
99