Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 777

PCI Express* Configuration Registers
19.1.30 LSTS—Link Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 52h–53h
Default Value:
Bit
15:14
13
12
11
10
9:4
3:0
Datasheet
See bit description
Reserved
Data Link Layer Active (DLLA) — RO. Default value is 0b.
0 = Data Link Control and Management State Machine is not in the DL_Active state
1 = Data Link Control and Management State Machine is in the DL_Active state
Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the PCH uses the
same reference clock as on the platform and does not generate its own clock.
Link Training (LT) — RO. Default value is 0b.
0 = Link training completed.
1 = Link training is occurring.
Link Training Error (LTE) — RO. Not supported. Set value is 0b.
Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the
given PCI Express* link. The contents of this NLW field is undefined if the link has not
successfully trained.
Port # Possible Values
1 000001b, 000010b, 000100b
2 000001b
3 000001b, 000010b
4 000001b
5 000001b, 000010b, 000100b
6 000001b
7 000001b, 000010b
8 000001b
NOTE: 000001b = x1 link width, 000010b =x2 linkwidth, 000100b = x4 linkwidth
Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI
Express* link.
0001b = Link is 2.5 Gb/s
0010b = Link is 5.0 Gb/s
Attribute: RO
Size: 16 bits
Description
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