Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 603

SATA Controller Registers (D31:F2)
14.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2)
Address Offset: Port 0: ABAR + 108h
Default Value:
Bit
FIS Base Address (FB) — R/W. Indicates the 32-bit base for received FISes. The
structure pointed to by this address range is 256 bytes in length. This address must be
31:8
256-byte aligned, as indicated by bits 31:3 being read/write.
Note that these bits are not reset on a Controller reset.
7:0 Reserved
14.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits
Register (D31:F2)
Address Offset: Port 0: ABAR + 10Ch
Default Value:
Bit
Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for
the received FIS base for this port.
31:0
Note that these bits are not reset on a Controller reset.
Datasheet
Port 1: ABAR + 188h
Port 2: ABAR + 208h (if port available; see
Port 3: ABAR + 288h (if port available; see
Port 4: ABAR + 308h
Port 5: ABAR + 388h
Undefined
Port 1: ABAR + 18Ch
Port 2: ABAR + 20Ch (if port available; see
Port 3: ABAR + 28Ch (if port available; see
Port 4: ABAR + 30Ch
Port 5: ABAR + 38Ch
Undefined
Attribute: R/W
Section
Section
Size: 32 bits
Description
Attribute: R/W
Section
Section
Size: 32 bits
Description
1.3)
1.3)
1.3)
1.3)
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