Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 566

14.1.28 MSIMA— Message Signaled Interrupt Message Address
(SATA–D31:F2)
Address Offset: 84h
Default Value:
Note: There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Bits
Address (ADDR) — R/W. Lower 32 bits of the system specified message address,
31:2
always DWORD aligned.
1:0 Reserved
14.1.29 MSIMD—Message Signaled Interrupt Message Data
(SATA–D31:F2)
Address Offset: 88h–89h
Default Value:
Note: There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Bits
Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is
enabled. Its content is driven onto the lower word of the data bus of the MSI memory
15:0 write transaction. Note that when the MME field is set to '001' or '010', bit [0] and bits
[1:0] respectively of the MSI memory write transaction will be driven based on the
source of the interrupt rather than from MD[2:0]. See the description of the MME field.
566
87h
–
00000000h
0000h
SATA Controller Registers (D31:F2)
Attribute: R/W
Size: 32 bits
Description
Attribute: R/W
Size: 16 bits
Description
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