Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 508

13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)
Offset Address: A2h
Default Value:
Lockable:
Bit
DRAM Initialization Bit — R/W. This bit does not affect hardware functionality in any
way. BIOS is expected to set this bit prior to starting the DRAM initialization sequence
and to clear this bit after completing the DRAM initialization sequence. BIOS can detect
that a DRAM initialization sequence was interrupted by a reset by reading this bit during
7
the boot sequence.
6 Reserved
Memory Placed in Self-Refresh (MEM_SR) — RO.
5
System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.
0 = SYS_RESET# button Not pressed.
1 = PCH sets this bit when the SYS_RESET# button is pressed. BIOS is expected to
4
NOTES:
1.
2.
Processor Thermal Trip Status (CTS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the
3
NOTES:
1.
2.
Minimum SLP_S4# Assertion Width Violation Status — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time
2
NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some
508
00h
No
• If the bit is 1, then the DRAM initialization was interrupted.
• This bit is reset by the assertion of the RSMRST# pin.
• If the bit is 1, DRAM should have remained powered and held in Self-Refresh
through the last power state transition (that is, the last time the system left S0).
• This bit is reset by the assertion of the RSMRST# pin.
read this bit and clear it, if it is set.
This bit is also reset by RSMRST# and CF9h resets.
The SYS_RESET# is implemented in the Main power well. This pin must be
properly isolated and masked to prevent incorrectly setting this Suspend well
status bit.
system is in an S0 or S1 state.
This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the
shutdown and reboot associated with the processor THRMTRIP# event.
The CF9h reset in the description refers to CF9h type core well reset which
includes SYS_RESET#, PWROK/SYS_PWROK low, SMBus hard reset, TCO
Timeout. This type of reset will clear CTS bit.
programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset
A4h:bits 5:4). The PCH begins the timer when SLP_S4# is asserted during S4/S5
entry or when the RSMRST# input is deasserted during SUS well power-up. Note
that this bit is functional regardless of the values in the SLP_S4# Assertion Stretch
Enable (D31:F0:Offset A4h:bit 3) and in the Disable SLP Stretching after SUS Well
Power Up (D31:F0:Offset A4h:bit 12).
cases before the default value is readable.
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W, RO, R/WC
Size: 8-bit
Usage: ACPI, Legacy
Power Well: Resume
Description
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