Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 574

14.1.38 FLRC—FLR Control (SATA–D31:F2)
Address Offset: B4–B5h
Default Value:
Bit
15:9 Reserved.
Transactions Pending (TXP) — RO.
8 0 = Controller has received all non-posted requests.
1 = Controller has issued non-posted requests which has not been completed.
7:1 Reserved.
Initiate FLR — R/W. Used to initiate FLR transition. A write of 1 indicates FLR
0 transition. Since hardware must not respond to any cycles till FLR completion the value
read by software from this bit is 0.
14.1.39 ATC—APM Trapping Control Register (SATA–D31:F2)
Address Offset: C0h
Default Value:
Function Level Reset:No
.
Bit
7:4 Reserved
Secondary Slave Trap (SST) — R/W. Enables trapping and SMI# assertion on legacy
3 I/O accesses to 170h–177h and 376h. The active device on the secondary interface
must be device 1 for the trap and/or SMI# to occur.
Secondary Master Trap (SPT) — R/W. Enables trapping and SMI# assertion on
2 legacy I/O accesses to 170h-177h and 376h. The active device on the secondary
interface must be device 0 for the trap and/or SMI# to occur.
Primary Slave Trap (PST) — R/W. Enables trapping and SMI# assertion on legacy I/
1 O accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be
device 1 for the trap and/or SMI# to occur.
Primary Master Trap (PMT) — R/W. Enables trapping and SMI# assertion on legacy
0 I/O accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must
be device 0 for the trap and/or SMI# to occur.
574
0000h
00h
SATA Controller Registers (D31:F2)
Attribute: RO, R/W
Size: 16 bits
Description
Attribute: R/W
Size: 8 bits
Description
Datasheet