Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 831

Serial Peripheral Interface (SPI)
21.1.30 SRDL — Soft Reset Data Lock
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Bit
31:1 Reserved.
Set_Stap Lock (SSL) — R/WL.
0 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers
0
1 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers
NOTE: That this bit is reset to '0' on CF9h resets.
21.1.31 SRDC — Soft Reset Data Control
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Bit
31:1 Reserved.
Soft Reset Data Select (SRDS) — R/WL.
0 = The Set_Strap data sends the default processor configuration data.
1 = The Set_Strap message bits come from the Set_Strap Msg Data register.
0
NOTES:
1.
2.
21.1.32 SRD — Soft Reset Data
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Bit
31:14 Reserved.
Set_Stap Data (SSD) — R/WL.
NOTES:
13:0
1.
2.
Datasheet
SPIBAR + F0h
00000000h
are writeable.
are locked.
SPIBAR + F4h
00000000h
This bit is reset by the RSMRST# or when the Resume well loses power.
This bit is locked by the SSL bit (SPIBAR+F0h:bit 0).
SPIBAR + F8h
00000000h
These bits are reset by the RSMRST#, or when the Resume well loses power.
These bits are locked by the SSL bit (SPIBAR+F0h:bit 0).
Attribute: R/WL
Size: 32 bits
Description
Attribute: R/WL
Size: 32 bits
Description
Attribute: R/WL
Size: 32 bits
Description
831