Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 880

23.2.1 VID—Vendor Identification Register
(MEI—D22:F1)
Address Offset: 00h
Default Value:
Bit
15:0 Vendor ID (VID) — RO. This is a 16-bit value assigned to Intel.
23.2.2 DID—Device Identification Register
(MEI—D22:F1)
Address Offset: 02h–03h
Default Value:
Bit
Device ID (DID) — RO. This is a 16-bit value assigned to the Intel Management
15:0 Engine Interface controller. See the Intel
value of the DID Register.
23.2.3 PCICMD—PCI Command Register
(MEI—D22:F1)
Address Offset: 04h–05h
Default Value:
Bit
15:11 Reserved
Interrupt Disable (ID) — R/W. Disables this device from generating PCI line based
10
interrupts. This bit does not have any effect on MSI operation.
9:3 Reserved
Bus Master Enable (BME)— R/W. Controls the Intel MEI host controller's ability to act
as a system memory master for data transfers. When this bit is cleared, Intel MEI bus
master activity stops and any active DMA engines return to an idle condition. This bit is
made visible to firmware through the H_PCI_CSR register, and changes to this bit may
be configured by the H_PCI_CSR register to generate an ME MSI. When this bit is 0,
2
Intel MEI is blocked from generating MSI to the host processor.
NOTE: This bit does not block Intel MEI accesses to ME-UMA; that is, writes or reads to
Memory Space Enable (MSE) — R/W. Controls access to the Intel ME's memory
mapped register space.
0 = Disable. Memory cycles within the range specified by the memory base and limit
1
1 = Enable. Allows memory cycles within the range specified by the memory base and
0 Reserved
880
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
01h
–
8086h
See bit description
0000h
the host and ME circular buffers through the read window and write window
registers still cause ME backbone transactions to ME-UMA.
registers are master aborted.
limit registers accepted.
Attribute: RO
Size: 16 bits
Description
Attribute: RO
Size: 16 bits
Description
®
6 Series Chipset Specification Update for the
Attribute: R/W, RO
Size: 16 bits
Description
Datasheet