Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 405

Chipset Configuration Registers
Bit
22
21
20
19
18
17
16
15
14
13
12:5
Datasheet
PCI Express 7 Disable (PE7D) — R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
0 = PCI Express port #7 is enabled.
1 = PCI Express port #7 is disabled.
PCI Express* 6 Disable (PE6D) — R/W. Default is 0. When disabled, the link for
this port is put into the "link down" state.
0 = PCI Express* port #6 is enabled.
1 = PCI Express port #6 is disabled.
PCI Express 5 Disable (PE5D) — R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
0 = PCI Express port #5 is enabled.
1 = PCI Express port #5 is disabled.
PCI Express 4 Disable (PE4D) — R/W. Default is 0. When disabled, the link for this
port is put into the "link down" state.
0 = PCI Express port #4 is enabled.
1 = PCI Express port #4 is disabled.
NOTE: This bit must be set when Port 1 is configured as a x4.
PCI Express 3 Disable (PE3D) — R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
0 = PCI Express port #3 is enabled.
1 = PCI Express port #3 is disabled.
NOTE: This bit must be set when Port 1 is configured as a x4.
PCI Express 2 Disable (PE2D) — R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
0 = PCI Express port #2 is enabled.
1 = PCI Express port #2 is disabled.
NOTE: This bit must be set when Port 1 is configured as a x4 or a x2.
PCI Express 1 Disable (PE1D) — R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
0 = PCI Express port #1 is enabled.
1 = PCI Express port #1 is disabled.
EHCI #1 Disable (EHCI1D) — R/W. Default is 0.
0 = The EHCI #1 is enabled.
1 = The EHCI #1 is disabled.
LPC Bridge Disable (LBD) — R/W. Default is 0.
0 = The LPC bridge is enabled.
1 = The LPC bridge is disabled. Unlike the other disables in this register, the following
additional spaces will no longer be decoded by the LPC bridge:
• · Memory cycles below 16 MB (1000000h)
• · I/O cycles below 64 KB (10000h)
• · The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF
Memory cycle in the LPC BIOS range below 4 GB will still be decoded when this bit is
set; however, the aliases at the top of 1 MB (the E and F segment) no longer will be
decoded.
EHCI #2 Disable (EHCI2D) — R/W. Default is 0.
0 = The EHCI #2 is enabled.
1 = The EHCI #2 is disabled.
Reserved
Description
405