Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 539

LPC Interface Bridge Registers (D31:F0)
13.9.7 TCO2_CNT—TCO2 Control Register
I/O Address:
Default Value:
Lockable:
Bit
15:6
5:4
3
2:1
0
13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers
I/O Address:
Default Value:
Lockable:
Bit
7:0
Datasheet
TCOBASE +0Ah
0008h
No
Reserved
OS_POLICY — R/W. OS-based software writes to these bits to select the policy that
the BIOS will use after the platform resets due the WDT. The following convention is
recommended for the BIOS and OS:
00 = Boot normally
01 = Shut down
10 = Do not load OS. Hold in pre-boot state and use LAN to determine next step
11 = Reserved
NOTE: These are just scratchpad bits. They should not be reset when the TCO logic
resets the platform due to Watchdog Timer.
GPIO11_ALERT_DISABLE — R/W. At reset (using RSMRST# asserted) this bit is set
and GPIO[11] alerts are disabled.
0 = Enable.
1 = Disable GPIO11/SMBALERT# as an alert source for the heartbeats and the SMBus
slave.
INTRD_SEL — R/W. This field selects the action to take if the INTRUDER# signal goes
active.
00 = No interrupt or SMI#
01 = Interrupt (as selected by TCO_INT_SEL).
10 = SMI
11 = Reserved
Reserved
TCOBASE +0Ch (Message 1)Attribute:
TCOBASE +0Dh (Message 2)
00h
No
TCO_MESSAGE[n] — R/W. BIOS can write into these registers to indicate its boot
progress. The external microcontroller can read these registers to monitor the boot
progress.
Attribute: R/W
Size: 16-bit
Power Well: Resume
Description
R/W
Size: 8-bit
Power Well: Resume
Description
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