Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 615

SATA Controller Registers (D31:F2)
14.4.2.13 PxSACT—Port [5:0] Serial ATA Active (D31:F2)
Address Offset: Port 0: ABAR + 134h
Default Value:
Bit
Device Status (DS) — R/W. System software sets this bit for SATA queuing operations
prior to setting the PxCI.CI bit in the same command slot entry. This field is cleared
using the Set Device Bits FIS.
31:0
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is
cleared by software, and as a result of a COMRESET or SRST.
14.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2)
Address Offset: Port 0: ABAR + 138h
Default Value:
Bit
Commands Issued (CI) — R/W. This field is set by software to indicate to the PCH
that a command has been built-in system memory for a command slot and may be sent
to the device. When the PCH receives a FIS which clears the BSY and DRQ bits for the
command, it clears the corresponding bit in this register for that command slot. Bits in
31:0
this field shall only be set to 1 by software when PxCMD.ST is set to 1.
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is
cleared by software.
Datasheet
Port 1: ABAR + 1B4h
Port 2: ABAR + 234h (if port available; see
Port 3: ABAR + 2B4h (if port available; see
Port 4: ABAR + 334h
Port 5: ABAR + 3B4h
00000000h
Port 1: ABAR + 1B8h
Port 2: ABAR + 238h (if port available; see
Port 3: ABAR + 2B8h (if port available; see
Port 4: ABAR + 338h
Port 5: ABAR + 3B8h
00000000h
Attribute: R/W
Section
Section
Size: 32 bits
Description
Attribute: R/W
Section
Section
Size: 32 bits
Description
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