Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 514

13.8.1.8 PMIR—Power Management Initialization Register (PM—D31:F0)
Offset Address: ACh
Default Value:
0
Bit
CF9h Lockdown (CF9LOCK) — R/W.
0 = CF9h Global Reset bit R/W.
31 1 = CF9h Global Reset bit RO.
In manufacturing/debug environments this bit should be left as default 0b. In all other
environments, BIOS must program this bit to 1b.
30:26 Reserved.
SLP_LAN# Low on DC Power (SLP_LAN_LOW_DC) — R/W.
When set to '1' and the platform is on DC power (ACPRESENT deasserted), the PCH will
drive SLP_LAN# low while in Sx/Moff even if the host and Intel ME policy bits indicate
25
that the PHY should remain powered. If the platform subsequently switches to AC
power (ACPRESENT asserts), SLP_LAN# will be driven high and the PCH will re-
configure the PHY for Wake on Magic Packet.
24:21 Reserved.
CF9h Global Reset (CF9GR)— R/W.
When set, a CF9h write of 6h or Eh will cause a Global reset of both the Host and Intel
20
ME partitions. If this bit is cleared, a CF9h write of 6h or Eh will only reset the host
partition. This bit field is not reset by a CF9h reset.
19:0 Reserved.
13.8.1.9 GPIO_ROUT—GPIO Routing Control Register
(PM—D31:F0)
Offset Address: B8h – BBh
Default Value:
Lockable:
Bit
31:30 GPIO15 Route — R/W. See bits 1:0 for description.
5:4 GPIO2 Route — R/W. See bits 1:0 for description.
3:2 GPIO1 Route — R/W. See bits 1:0 for description.
GPIO0 Route — R/W. GPIO can be routed to cause an NMI, SMI# or SCI when the
GPIO[n]_STS bit is set. If the GPIO0 is not set to an input, this field has no effect.
If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPIO can
cause a Wake event, even if the GPIO is NOT routed to cause an NMI, SMI# or SCI.
1:0
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
10 = SCI (if corresponding GPE0_EN bit is also set)
11 = NMI (If corresponding GPI_NMI_EN is also set)
Note: GPIOs that are not implemented will not have the corresponding bits implemented in
this register.
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00000000h
00000000h
No
Same pattern for GPIO14 through GPIO3
LPC Interface Bridge Registers (D31:F0)
Attribute: R/W
Size: 32-bit
Description
Attribute: R/W
Size: 32-bit
Power Well: Resume
Description
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