Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 826

21.1.23 BBAR—BIOS Base Address Configuration Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Eight entries are available in this register to give BIOS a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
Bit
31:24 Reserved
Bottom of System Flash— R/W. This field determines the bottom of the System
BIOS. The PCH will not run programmed commands nor memory reads whose address
field is less than this value. this field corresponds to bits 23:8 of the 3-byte address;
bits 7:0 are assumed to be 00h for this vector when comparing to a potential SPI
address.
23:8
NOTE: The SPI host controller prevents any programmed cycle using the address
7:0 Reserved
21.1.24 FDOC—Flash Descriptor Observability Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address:
Default Value:
Note: This register that can be used to observe the contents of the Flash Descriptor that is
stored in the PCH Flash Controller. This register is only applicable when SPI device is in
descriptor mode.
Bit
31:15 Reserved
Flash Descriptor Section Select (FDSS) — R/W. Selects which section within the
loaded Flash Descriptor to observe.
000 = Flash Signature and Descriptor Map
001 = Component
14:12
010 = Region
011 = Master
111 = Reserved
Flash Descriptor Section Index (FDSI) — R/W. Selects the DW offset within the
11:2
Flash Descriptor Section to observe.
1:0 Reserved
826
SPIBAR + A0h
00000000h
register with an address less than the value in this register. Some flash devices
specify that the Read ID command must have an address of 0000h or 0001h. If
this command must be supported with these devices, it must be performed with
the BIOS BAR.
SPIBAR + B0h
00000000h
Serial Peripheral Interface (SPI)
Attribute: R/W, RO
Size: 32 bits
Description
Attribute: R/W
Size: 32 bits
Description
Datasheet