Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 512

13.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration
Lock Register
Offset Address: A6h
Default Value:
Lockable:
Power Well:
Bit
7:3
2
1
0
C
13.8.1.5 Chipset Initialization Register 4 (PM—D31:F0)
Offset Address: A9h
Default Value:
Lockable:
Power Well:
Bit
7:0 CIR4 Field 1 — R/W. BIOS must program this field to 47h.
512
00h
No
Core
Reserved
SLP Stretching Policy Lock-Down (SLP_STR_POL_LOCK) — R/WLO. When set
to 1, this bit locks down the Disable SLP Stretching After SUS Well Power Up,
SLP_S3# Minimum Assertion Width, SLP_S4# Minimum Assertion Width, SLP_S4#
Assertion Stretch Enable bits in the GEN_PMCON_3 register, making them read-
only.
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit
are always ignored.
This bit is cleared by platform reset.
ACPI_BASE_LOCK — R/WLO. When set to 1, this bit locks down the ACPI Base
Address Register (ABASE) at offset 40h. The Base Address Field becomes read-
only.
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit
are always ignored. Once locked by writing 1, the only way to clear this bit is to
perform a platform reset.
Reserved
03h
No
Core
LPC Interface Bridge Registers (D31:F0)
Attribute: RO, R/WLO
Size: 8-bit
Usage: ACPI
Description
Attribute: R/W
Size: 8-bit
Usage: ACPI, Legacy
Description
Datasheet