Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 425

PCI-to-PCI Bridge Registers (D30:F0)
11.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)
Offset Address: 3Eh
Default Value:
Bit
15:12
11
10
9
8
7
6
5
4
Datasheet
3Fh
–
0000h
Reserved
Discard Timer SERR# Enable (DTE) — R/W. Controls the generation of SERR# on
the primary interface in response to the DTS bit being set:
0 = Do not generate SERR# on a secondary timer discard
1 = Generate SERR# in response to a secondary timer discard
Discard Timer Status (DTS) — R/WC. This bit is set to 1 when the secondary discard
timer (see the SDT bit below) expires for a delayed transaction in the hard state.
Secondary Discard Timer (SDT) — R/W. This bit sets the maximum number of PCI
clock cycles that the PCH waits for an initiator on PCI to repeat a delayed transaction
request. The counter starts once the delayed transaction data is has been returned by
the system and is in a buffer in the PCH PCI bridge. If the master has not repeated the
transaction at least once before the counter expires, the PCH PCI bridge discards the
transaction from its queue.
0 = The PCI master timeout value is between 2
1 = The PCI master timeout value is between 2
Primary Discard Timer (PDT) — R/W. This bit is R/W for software compatibility only.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The PCI logic will not generate
fast back-to-back cycles on the PCI bus.
Secondary Bus Reset (SBR) — R/W. Controls PCIRST# assertion on PCI.
0 = Bridge deasserts PCIRST#
1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction
buffers, posting buffers, and the PCI bus are initialized back to reset conditions.
The rest of the part and the configuration registers are not affected.
Master Abort Mode (MAM) — R/W. Controls the PCH PCI bridge's behavior when a
master abort occurs:
Master Abort on processor /PCH Interconnect (DMI):
0 = Bridge asserts TRDY# on PCI. It drives all 1s for reads, and discards data on writes.
1 = Bridge returns a target abort on PCI.
Master Abort PCI (non-locked cycles):
0 = Normal completion status will be returned on the processor/PCH interconnect.
1 = Target abort completion status will be returned on the processor/PCH interconnect.
NOTE: All locked reads will return a completer abort completion status on the
processor/PCH interconnect.
VGA 16-Bit Decode (V16D) — R/W. Enables the PCH PCI bridge to provide 16-bits
decoding of VGA I/O address precluding the decode of VGA alias addresses every 1 KB.
This bit requires the VGAE bit in this register be set.
Attribute: R/WC, RO, R/W
Size: 16 bits
Description
15 16
and 2 PCI clocks
10 11
and 2 PCI clocks
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