Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 370

10.1.16 CIR32—Chipset Initialization Register 32
Offset Address: 2040–2043h
Default Value:
Bit
31:0
10.1.17 CIR1—Chipset Initialization Register 1
Offset Address: 2088–208Bh
Default Value:
Bit
31:21
20
19:16
15
14:13
12
11:0
10.1.18 REC—Root Error Command Register
Offset Address: 20AC–20AFh
Default Value:
Bit
31
30:0
370
00000000h
CIR32 Field 0— R/WL. BIOS must set this field. These bits are locked if the
TCLOCKDN bit (RCBA+0050h:bit 31) is set.
00000000h
Reserved
CIR1 Field 3 — R/WO. BIOS must set this bit.
Reserved
CIR1 Field 2 — R/WO. BIOS must set this bit.
Reserved
CIR1 Field 1— R/WO. BIOS must set this bit.
Reserved
0000h
Drop Poisoned Downstream Packets (DPDP) — R/W. Determines how
downstream packets on DMI are handled that are received with the EP field set,
indicating poisoned data:
0 = Packets are forwarded downstream without forcing the UT field set.
1 = This packet and all subsequent packets with data received on DMI for any VC will
have their Unsupported Transaction (UT) field set causing them to master Abort
downstream. Packets without data such as memory, I/O and config read requests
are allowed to proceed.
Reserved
Chipset Configuration Registers
Attribute: R/WL, RO
Size: 32-bit
Description
Attribute: R/WO
Size: 32-bit
Description
Attribute: R/W
Size: 32-bit
Description
Datasheet