Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 602

14.4.2.1 PxCLB—Port [5:0] Command List Base Address Register
(D31:F2)
Address Offset: Port 0: ABAR + 100h
Default Value:
Bit
Command List Base Address (CLB) — R/W. Indicates the 32-bit base for the
command list for this port. This base is used when fetching commands to execute. The
structure pointed to by this address range is 1 KB in length. This address must be 1-KB
31:10
aligned as indicated by bits 31:10 being read/write.
Note that these bits are not reset on a Controller reset.
9:0 Reserved
14.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper
32-Bits Register (D31:F2)
Address Offset: Port 0: ABAR + 104h
Default Value:
Bit
Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for
the command list base address for this port. This base is used when fetching
31:0
commands to execute.
Note that these bits are not reset on a Controller reset.
602
Port 1: ABAR + 180h
Port 2: ABAR + 200h (if port available; see
Port 3: ABAR + 280h (if port available; see
Port 4: ABAR + 300h
Port 5: ABAR + 380h
Undefined
Port 1: ABAR + 184h
Port 2: ABAR + 204h (if port available; see
Port 3: ABAR + 284h (if port available; see
Port 4: ABAR + 304h
Port 5: ABAR + 384h
Undefined
SATA Controller Registers (D31:F2)
Attribute: R/W
Section
Section
Size: 32 bits
Description
Attribute: R/W
Section
Section
Size: 32 bits
Description
1.3)
1.3)
1.3)
1.3)
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