Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 803

High Precision Event Timer Registers
20.1.5 TIMn_CONF—Timer n Configuration and Capabilities
Register
Address Offset: Timer 0:
Default Value:
Note: The letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 referring to Timer 0, 1, 2, 3, 4, 5, 6, or 7.
Bit
63:56
55:52,
43
51:45,
42:16
15
14
Datasheet
100–107h,
Timer 1: 120–127h,
Timer 2: 140–147h,
Timer 3: 160–167h,
Timer 4: 180–187h,
Timer 5: 1A0–1A7h,
Timer 6: 1C0–1C7h,
Timer 7: 1E0–1E7h,
N/A
Reserved. These bits will return 0 when read.
Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP) — RO.
Timer 0, 1:Bits 52, 53, 54, and 55 in this field (corresponding to IRQ 20, 21, 22, and
23) have a value of 1. Writes will have no effect.
Timer 2:Bits 43, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22,
and 23) have a value of 1. Writes will have no effect.
Timer 3:Bits 44, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22,
and 23) have a value of 1. Writes will have no effect.
Timer 4, 5, 6, 7:This field is always 0 as interrupts from these timers can only be
delivered using direct processor interrupt messages.
NOTE: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared
with any other devices to ensure the proper operation of HPET #2.
NOTE: If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared
with any other devices to ensure the proper operation of HPET #3.
Reserved. These bits return 0 when read.
Timer n Processor Message Interrupt Delivery (Tn_PROCMSG_INT_DEL_CAP) — RO.
This bit is always read as '1', since the PCH HPET implementation supports the direct
processor interrupt delivery.
Timer n Processor Message Interrupt Enable (Tn_PROCMSG_EN_CNF) — R/W
/ RO. If the Tn_PROCMSG_INT_DEL_CAP bit is set for this timer, then the software
can set the Tn_PROCMSG_EN_CNF bit to force the interrupts to be delivered directly
as processor messages, rather than using the 8259 or I/O (x) APIC. In this case, the
Tn_INT_ROUT_CNF field in this register will be ignored. The Tn_PROCMSG_ROUT
register will be used instead.
Timer 0, 1, 2, 3 Specific: This bit is a read/write bit.
Timer 4, 5, 6, 7 Specific: This bit is always Read Only '1' as interrupt from these
timers can only be delivered using direct processor interrupt messages.
Attribute: RO, R/W
Size: 64 bit
Description
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