Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 715

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Integrated Intel High Definition Audio Controller Registers
17.1.2.12 INTCTL—Interrupt Control Register
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(Intel
Memory Address:HDBAR + 20h
Default Value:
Bit
Global Interrupt Enable (GIE) — R/W. Global bit to enable device interrupt
generation.
1 = When set to 1, the Intel High Definition Audio function is enabled to generate an
31
NOTE: This bit is not affected by the D3
Controller Interrupt Enable (CIE) — R/W. Enables the general interrupt for
controller functions.
1 = When set to 1, the controller generates an interrupt when the corresponding status
30
NOTE: This bit is not affected by the D3
29:8 Reserved
Stream Interrupt Enable (SIE) — R/W. When set to 1, the individual streams are
enabled to generate an interrupt when the corresponding status bits get set.
A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry
being completed, or as a result of a FIFO error (underrun or overrun) occurring. Control
over the generation of each of these sources is in the associated Stream Descriptor.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
7:0
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
Datasheet
High Definition Audio Controller—D27:F0)
00000000h
interrupt. This control is in addition to any bits in the bus specific address space,
such as the Interrupt Enable bit in the PCI configuration space.
bit gets set due to a Response Interrupt, a Response Buffer Overrun, and State
Change events.
Attribute: R/W
Size: 32 bits
Description
to D0 transition.
HOT
to D0 transition.
HOT
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