Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 4

5.2.4.4
5.3 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 122
5.3.1 GbE PCI Express* Bus Interface.............................................................. 124
5.3.1.1
5.3.1.2
5.3.1.3
5.3.2 Error Events and Error Reporting ............................................................ 124
5.3.2.1
5.3.2.2
5.3.3 Ethernet Interface ................................................................................ 125
5.3.3.1
5.3.4 PCI Power Management ......................................................................... 125
5.3.4.1
5.3.5 Configurable LEDs................................................................................. 127
5.3.6 Function Level Reset Support (FLR) ......................................................... 128
5.3.6.1
5.4 LPC Bridge (with System and Management Functions) (D31:F0)............................. 129
5.4.1 LPC Interface ....................................................................................... 129
5.4.1.1
5.4.1.2
5.4.1.3
5.4.1.4
5.4.1.5
5.4.1.6
5.4.1.7
5.4.1.8
5.4.1.9
5.4.1.10 Bus Master Cycles ................................................................... 133
5.4.1.11 LPC Power Management ........................................................... 133
5.4.1.12 Configuration and PCH Implications ........................................... 133
5.5 DMA Operation (D31:F0) .................................................................................. 134
5.5.1 Channel Priority.................................................................................... 134
5.5.1.1
5.5.1.2
5.5.2 Address Compatibility Mode ................................................................... 135
5.5.3 Summary of DMA Transfer Sizes ............................................................. 135
5.5.3.1
5.5.4 Autoinitialize ........................................................................................ 136
5.5.5 Software Commands ............................................................................. 136
5.6 LPC DMA ........................................................................................................ 137
5.6.1 Asserting DMA Requests ........................................................................ 137
5.6.2 Abandoning DMA Requests..................................................................... 137
5.6.3 General Flow of DMA Transfers ............................................................... 138
5.6.4 Terminal Count..................................................................................... 138
5.6.5 Verify Mode ......................................................................................... 138
5.6.6 DMA Request Deassertion ...................................................................... 139
5.6.7 SYNC Field / LDRQ# Rules ..................................................................... 139
5.7 8254 Timers (D31:F0) ...................................................................................... 140
5.7.1 Timer Programming .............................................................................. 141
5.7.2 Reading from the Interval Timer ............................................................. 142
5.7.2.1
5.7.2.2
5.7.2.3
5.8 8259 Interrupt Controllers (PIC) (D31:F0)........................................................... 143
5.8.1 Interrupt Handling ................................................................................ 144
5.8.1.1
5.8.1.2
5.8.1.3
5.8.2 Initialization Command Words (ICWx) ..................................................... 145
5.8.2.1
5.8.2.2
5.8.2.3
5.8.2.4
5.8.3 Operation Command Words (OCW) ......................................................... 146
5.8.4 Modes of Operation ............................................................................... 146
5.8.4.1
5.8.4.2
4
SMI/SCI Generation................................................................. 122
Transaction Layer.................................................................... 124
Data Alignment ....................................................................... 124
Configuration Request Retry Status ........................................... 124
Data Parity Error ..................................................................... 124
Completion with Unsuccessful Completion Status ......................... 125
82579 LAN PHY Interface ......................................................... 125
Wake Up ................................................................................ 126
FLR Steps............................................................................... 128
LPC Cycle Types ...................................................................... 130
Start Field Definition ................................................................ 130
Cycle Type / Direction (CYCTYPE + DIR)..................................... 131
Size....................................................................................... 131
SYNC..................................................................................... 132
SYNC Time-Out ....................................................................... 132
SYNC Error Indication .............................................................. 132
LFRAME# Usage...................................................................... 132
I/O Cycles .............................................................................. 133
Fixed Priority .......................................................................... 134
Rotating Priority ...................................................................... 135
Address Shifting When Programmed for 16-Bit I/O Count by Words 135
Simple Read ........................................................................... 142
Counter Latch Command .......................................................... 142
Read Back Command ............................................................... 142
Generating Interrupts .............................................................. 144
Acknowledging Interrupts ......................................................... 144
Hardware/Software Interrupt Sequence...................................... 145
ICW1..................................................................................... 145
ICW2..................................................................................... 146
ICW3..................................................................................... 146
ICW4..................................................................................... 146
Fully Nested Mode ................................................................... 146
Special Fully-Nested Mode ........................................................ 147
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