Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 112

Table 3-5. Power Plane for Input Signals for Mobile Configurations (Sheet 3 of 3)
Signal Name Power Well
CLKIN_DMI_P,
CLKIN_DMI_N
CLKIN_SATA_N/
CLKIN_SATA_P/
CLKIN_DOT_96P,
CLKIN_DOT_96N
CLKIN_PCILOOPBACK
PCIECLKRQ[7:3]#/
1
GPIO[46:44,26:25] ,
PCIECLKRQ0#/
1
GPIO73
PCIECLKRQ[2:1]#/
1
GPIO[20:18]
PEG_A_CLKRQ#/
1
GPIO47 ,
PEG_B_CLKRQ#/
1
GPIO56
XTAL25_IN
REFCLK14IN
CLKIN_PCILOOPBACK
FDI_RXP[7:0],
FDI_RXN[7:0]
DDP[B:C:D]_HPD
SDVO_INTP,
SDVO_INTN
SDVO_TVCLKINP,
SDVO_TVCLKINN
SDVO_STALLP,
SDVO_STALLN
NOTES:
1. These signals can be configured as outputs in GPIO mode.
2. This signal is sampled as a functional strap during Reset. Refer to Functional straps
definition table for usage.
3. External Termination is required for JTAG enabling.
4. Not all signals or pin functionalities may be available on a given SKU. See
Chapter 2
112
Driver During Reset
Clock Interface
Core External pull-down
Core External pull-down
Core External pull-down
Core Clock Generator
Suspend External Pull-up
Core External Pull-up
Suspend External Pull-up
Core Clock Generator
Core External pull-down
Core Clock Generator
®
Intel Flexible Display Interface
Core Processor
Digital Display Interface
Core External Pull-down
Core SDVO controller device
Core SDVO controller device
Core SDVO controller device
for details.
C-x
S0/S1
states
Low Low
Low Low
Low Low
Running Running
Driven Driven
Driven Driven
Driven Driven
High-Z High-Z
Low Low
High-Z High-Z
Driven Driven
Driven Driven
Driven Driven
Driven Driven
Driven Driven
§ §
PCH Pin States
S3 S4/S5
Off Off
Off Off
Off Off
Off Off
Driven Driven
Off Off
Driven Driven
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Off Off
Section 1.3 and
Datasheet