Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 637

SATA Controller Registers (D31:F5)
15.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5)
Address Offset:
Default Value:
SDATA when SINDX.RIDX is 00h. This is a 32-bit register that conveys the current state
of the interface and host. The PCH updates it continuously and asynchronously. When
the PCH transmits a COMRESET to the device, this register is updated to its reset
values.
Bit
31:12 Reserved
Interface Power Management (IPM) — RO. Indicates the current interface state:
11:8
All other values reserved.
Current Interface Speed (SPD) — RO. Indicates the negotiated interface
communication speed.
7:4
All other values reserved.
The PCH Supports Gen 1 communication rates (1.5 Gb/s), Gen 2 rates
(3.0 Gb/s)
Device Detection (DET) — RO. Indicates the interface device detection and Phy
state:
3:0
All other values reserved.
Datasheet
00000000h
Value Description
0h Device not present or communication not established
1h Interface in active state
2h Interface in PARTIAL power management state
6h Interface in SLUMBER power management state
Value Description
0h Device not present or communication not established
1h Generation 1 communication rate negotiated
2h Generation 2 communication rate negotiated
Value Description
0h No device detected and Phy communication not established
1h Device presence detected but Phy communication not established
3h Device presence detected and Phy communication established
Phy in offline mode as a result of the interface being disabled or
4h
running in a BIST loopback mode
Attribute: RO
Size: 32 bits
Description
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