Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Datasheet page 473

LPC Interface Bridge Registers (D31:F0)
13.1.38.4 FVEC3—Feature Vector Register 3
FVECIDX.IDX:
Default Value:
Bit
31:14
13
12
11:0
13.1.39 RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)
Offset Address: F0–F3h
Default Value:
Bit
31:14
13:1
0
Datasheet
0011b
See Description
Reserved
Data Center Manageability Interface (DCMI) Capability — RO
0 = Capable
1 = Disabled
Node Manager Capability — RO
0 = Capable
1 = Disabled
Reserved
00000000h
Base Address (BA) — R/W. Base Address for the root complex register block decode
range. This address is aligned on a 16-KB boundary.
Reserved
Enable (EN) — R/W. When set, this bit enables the range specified in BA to be claimed
as the Root Complex Register Block.
Attribute: RO
Size: 32 bit
Power Well: Core
Description
Attribute: R/W
Size: 32 bit
Description
473